1. Field of the Invention
The invention relates to the field of driver circuits, especially balanced driver stages having push-pull transistors as used to drive television scan velocity modulation (SVM) coils and similar loads.
2. Description of Related Art
Driver circuits such as television scan velocity modulation (SVM) driver stages, also referred to as beam scan velocity modulation (BSVM), frequently use push-pull transistor current source circuits to drive SVM coils on the picture tube with a current signal derived from the video signal being displayed. The SVM coils can be driven directly in one output amplification stage, or a somewhat lower power push-pull transistor current source driver can be coupled to a higher power stage such as a push-pull emitter follower that drives the SVM coil.
The SVM coil is driven to produce a magnetic field to supplement the main deflection fields for modulating beam scanning velocity in a manner that enhances the sharpness of transitions in video luminance. For example at transitions between dark and light areas, the beam is passed more slowly across the lighter area on the display, which appears brighter that it would otherwise, and more quickly across the darker part. The SVM drive signal is derived in part from the derivative of the luminance component of the video signal and also can be modulated by horizontal and vertical rate parabolas such that the effect on picture sharpness is equal at different positions on the display.
An SVM driver stage typically has sufficient power to drive currents at least on the order of .+-.1 amp and voltages on the order of .+-.50 volts in the SVM coil. The SVM driver must also function at video frequencies, for example up to 10 MHz for conventional NTSC, higher for noninterlaced scanning, and up to 40 MHz for high definition television.
FIG. 1, labeled as prior art, is a schematic representation of a conventional push-pull current driver output stage, as might drive an SVM coil. The SVM coil or other load 20 is to be driven from a DC power source Vdc according to an AC input signal Vac, which is AC coupled by capacitors C1 and C2 to the bases of complementary push-pull transistors Q1 and Q2. Transistors Q1 and Q2 are respectively NPN and PNP transistors and are operated oppositely. When transistor Q1 is off, transistor Q2 is on and provides current from source Vdc to the load, charging capacitor C3. When transistor Q2 is off, transistor Q1 is on and discharges capacitor C3 through the load. Resistors R1 through R6 provide bias. Capacitor C3, in series with the load, develops an average DC value such that the load can be driven at opposite polarities.
Driver stages of this type have high peak power requirements, but efficiency requires careful control of the DC collector current bias that flows through transistors Q1 and Q2. It is also advantageous to minimize distortion of the waveform. These interests lead to conflicting design requirements for the circuit.
A DC collector current bias is desirable through transistors Q1 and Q2, including some current conduction through the respective transistor Q1 or Q2 when it is quiescent, i.e., "off." This bias current preserves the small signal frequency response of the circuit and tends to reduce distortion of the signal through the stage. The quiescent collector current bias is typically on the order of 10 mA. Apart from avoiding distortion effects, it is generally not desirable to have unnecessary DC quiescent current draw, because this contributes directly to the quiescent power dissipation of the stage as a whole.
The DC supply voltage "Vdc" is typically about +140 volts DC. Assuming 10 mA quiescent collector current, the quiescent bias current causes power dissipation of about 1.4 watts (0.7 watts per transistor). At 50 mA, the quiescent power dissipation would be 7 Watts for the two transistors (3.5 watts each).
Despite the high peak power requirements needed to drive an SVM coil, the actual duty cycle is generally low. In some cases the duty cycle is controlled by feeding back a signal representative of the output stage supply current or power, which reduces the SVM signal amplitude for the relatively rare instances when higher power is called for. Thus, an efficient design takes advantage of the relatively low SVM duty cycle and sizes the output stage accordingly. It also is appropriate to minimize quiescent power dissipation in the push-pull current driver to avoid wasting power and to avoid the need for overly large heat sinks.
The conventional circuit of FIG. 1 is not particularly advantageous for controlling the quiescent DC current bias in transistors Q1 and Q2 (especially with changes in temperature of the transistors), because design choices for better limiting quiescent current have adverse operational effects. For example, resistors R5 and R6, in series with transistors Q1 and Q2, could be made large to obtain low quiescent current. Larger resistors provide a larger voltage drop as compared to the base-emitter voltages of the transistors, and thus reduce quiescent current dependence on Vbe and temperature. Alternatively or in addition, the remaining resistors R1 through R4 used to bias transistors Q1 and Q2 could be chosen to minimize quiescent current. If the designer chooses to make resistors R5 and R6 larger, excessively large resistor values may be needed. If the designer chooses to vary the bias via resistors R1 through R4 (i.e., to reduce quiescent current by making resistors R2, R3 larger, and resistors R1, R4 smaller), small signal response would suffer and cross-over distortion would be introduced.
For example, assuming that resistors R5 and R6 are to be sized to develop 0.5 volts at 10 mA quiescent loading for good temperature stability, their values would be 50 ohms. This is acceptable during quiescent conditions, but at .+-.1 amp peak drive current, resistors R5, R6 would develop a 50 volt peak drop. High power resistors would be needed. Moreover, it would be necessary to increase the supply voltage Vdc by as much as 100 volts to keep a high available peak voltage across the load in view of the voltage drop across the respective resistor R5 or R6. This solution for quiescent current limiting is incompatible with peak voltage and power dissipation requirements.
A possible refinement to the circuit of FIG. 1 is to add two Vbe compensating diodes, as shown in the emitter follower version of FIG. 2, also labeled as prior art. Where possible, the same reference designations are used in the respective figures to identify the same functional elements. One diode CR1 conducts in series with resistor R1 and one in series with resistor R4. The diode junction voltages are expected to match and compensate the base-emitter voltages of transistors Q1 and Q2. This is an improvement, but it does not eliminate problems associated with biasing the driver stage. For optimal performance and electrical efficiency it is necessary to match the diode junction voltages accurately to the transistor base-emitter voltages. The diodes must be thermally coupled to the heat sinks of transistors Q1 and Q2 to remain matched for tracking during thermal changes. Voltage matching can be improved by adjusting the current through the diodes or specifying a certain junction voltage of the diodes, but these techniques add to the cost of the circuit, as do the structures and manufacturing steps needed to accomplish thermal coupling of the diodes to the transistors.
Without special junction voltage matching and/or thermal tracking, a junction voltage mismatch can arise, especially with normal production variations. This mismatch can be on the order of .+-.100 mV, which is substantial because it requires a quiescent DC Voltage across resistors R1 and R4 of at least 200 mV for good repeatability and reasonable thermal stability. Resistors R5 and R6 then need to be 20 ohms for the case of a design center quiescent collector current of 10 mA. Quiescent current also could vary from 5 mA to 20 mA, given the assumed degree of mismatch. At .+-.1 amp output, resistors R5 and R6 would develop a peak voltage of 20 volts. This is an improvement over the original version of FIG. 1, wherein resistors R5, R6 developed a 50 volt peak, but still is inefficient.
The circuit of FIG. 2 represents a conventional audio driver having a push-pull emitter follower output stage. Although configured as an emitter follower, this circuit has the same limitations discussed above, including problems with maintaining low quiescent bias, bias stability, junction voltage matching, and relative inefficiency or less than optimal output drive voltage capability.